ROMAINE, JAMES BRIAN, ASHLEY, THOMAS IAN, PEREIRA MARTÍN, MARIO
No
IEEE Access
Article
Científica
3.9
0.926
30/06/2022
000838451100001
2-s2.0-85133796765
This article introduces a new multiplier-less 32-bit fixed point architecture for estimating complex non-linear functions based on adapted shift only series expansions. This novel hardware structure has been proposed for use as a dedicated core unit in implantable medical devices. Its implementation in FPGA produces a mean squared error of 0.23% over the functions <italic>sin</italic>(<italic>x</italic>),<italic>cos</italic>(<italic>x</italic>),<italic>eix</italic> and <italic>tan</italic>-1(<italic>x</italic>) when compared to unrestricted CPU implementations. These results are achieved with the use of only 133 sliced registers and 399 Look-up-tables (LUTs). Furthermore, the hardware performs extremely well in our hardware-in-the-loop real use case application for the detection of epilepsy by correctly detecting true positive seizures. When implemented into 130 nm technology via <italic>GOOGLE Sky130 PDK</italic> and <italic>Openlane</italic> EDA tools, the ASIC occupies a space of 0.0625 mm2 which represents a 47% reduction when compared to competitors. In addition, its power consumption is reduced to 6.46 mW at 100 MHz <italic>f<sub>o</sub></italic> and just 0.4 μW at 1KHz <italic>f<sub>o</sub></italic>. Author
Biomedical signal processing; Digital devices; Field programmable gate arrays (FPGA); Implants (surgical); Locks (fasteners); Low power electronics; Mathematical transformations; Table lookup; Timing circuits; Area optimization; Biomedical sensors; Epilepsy; Field programmable gate array; Field programmables; Functions approximations; Hardware; Hilbert transform; Implant; Low Power; Phase-Locking values; Power demands; Programmable gate array; Mean square error