Título High-Throughput Low Power Area Efficient 17-bit 2\'s Complement Multilayer Perceptron Components and Architecture for on-Chip Machine Learning in Implantable Devices
Publicación externa No
Medio IEEE Access
Alcance Article
Naturaleza Científica
Cuartil JCR 2
Cuartil SJR 1
Impacto JCR 3.9
Impacto SJR 0.926
Web https://www.scopus.com/inward/record.uri?eid=2-s2.0-85137605457&doi=10.1109%2fACCESS.2022.3203179&partnerID=40&md5=1211c001540639dd768ba3a7dbcc7bfd
Fecha de publicacion 31/08/2022
ISI 000873916300001
Scopus Id 2-s2.0-85137605457
DOI 10.1109/ACCESS.2022.3203179
Abstract In this manuscript the authors, design new hardware efficient combinational building blocks for a Multi Layer Perceptron (MLP) unit which eliminates the need for hardware generic Digital Signal Processing (DSP) units and also eliminates the need for on-chip block RAMs (BRAMs). The components were designed to minimise power and area consumption without sacrificing throughput. All designs were validated in a Field Programmable Gate Array (FPGA) and compared against unrestricted CPU-MATLAB implementations. Furthermore, a (2,2,2,2) MLP with back propagation was implemented and tested in a FPGA showing a total hardware utilisation of just 3782 LUTs, and no DSP or BRAMs. The MLP was also built in a Application Specific Integrated Circuit (ASIC) using a 130 nm technology by Skywater 130A. The results show that the area occupation was just 0.12~mm^{2} and consumed just 100 mW at 100 MHz input stimulus. © 2013 IEEE.
Palabras clave Application specific integrated circuits; Backpropagation; Deep neural networks; Digital signal processing; Field programmable gate arrays (FPGA); Implants (surgical); Integrated circuit design; Logic
Miembros de la Universidad Loyola

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