ROMAINE, JAMES BRIAN, Delgado-Restituto M. , Leñero-Bardallo J.A. , Rodríguez-Vázquez Á.
Si
Proc SPIE Int Soc Opt Eng
Conference Paper
Científica
0.234
01/01/2017
000423021200006
2-s2.0-85025581023
This paper reports a low area, low power, integer-based digital processor for the calculation of phase synchronization between two neural signals. The processor calculates the phase-frequency content of a signal by identifying the specific time periods associated with two consecutive minima. The simplicity of this phase-frequency content identifier allows for the digital processor to utilize only basic digital blocks, such as registers, counters, adders and subtractors, without incorporating any complex multiplication and or division algorithms. In fact, the processor, fabricated in a 0.18µm CMOS process, only occupies an area of 0.0625µm2 and consumes 12.5nW from a 1.2V supply voltage when operated at 128kHz. These low-area, low-power features make the proposed processor a valuable computing element in closed loop neural prosthesis for the treatment of neural diseases, such as epilepsy, or for extracting functional connectivity maps between different recording sites in the brain. © COPYRIGHT SPIE. Downloading of the abstract is permitted for personal use only.
Optical engineering; Complex multiplication; Digital processors; Division algorithms; Functional connectivity; Integrated systems; Low power CMOS; Phase synchronization; Seizure detection; CMOS integrated circuits