| Title |
Efficient FPGA Parallelization of Lipschitz Interpolation for Real-Time Decision-Making |
| Authors |
Nadales, J. M. , MANZANO CRESPO, JOSÉ MARÍA, Barriga, A. , Limon, D. |
| External publication |
No |
| Means |
IEEE Trans Control Syst Technol |
| Scope |
Article |
| Nature |
Científica |
| JCR Quartile |
2 |
| SJR Quartile |
1 |
| JCR Impact |
4.8 |
| SJR Impact |
1.985 |
| Web |
https://www.scopus.com/inward/record.uri?eid=2-s2.0-85122561199&doi=10.1109%2fTCST.2021.3136616&partnerID=40&md5=932041e7c5a3880cd4cc0d605fa7bfc4 |
| Publication date |
05/01/2022 |
| ISI |
000740073600001 |
| Scopus Id |
2-s2.0-85122561199 |
| DOI |
10.1109/TCST.2021.3136616 |
| Abstract |
One of the main open challenges in the field of learning-based control is the design of computing architectures able to process data in an efficient way. This is of particular importance when time constraints must be met, as, for instance, in real-time decision-making systems operating at high frequencies or when a vast amount of data must be processed. In this respect, field-programmable gate array (FPGA)-based parallel processing architectures have been hailed as a potential solution to this problem. In this article, a low-level design methodology for the implementation on FPGA platforms of Lipschitz interpolation (LI) algorithms is presented. The proposed design procedure exploits the potential parallelism of the LI algorithm and allows the user to optimize the area and energy resources of the resulting implementation. Besides, the proposed design allows to know in advance a tight bound of the error committed by the FPGA due to the representation format. Therefore, the resulting implementation is a highly parallelized and a fast architecture with an optimal use of the resources and consumption and with a fixed numerical error bound. These facts flawlessly suit the desirable specifications of learning-based control devices. As an illustrative case study, the proposed algorithm and architecture have been used to learn a nonlinear model predictive control law applied to self-balance a two-wheel robot. The results show how computational times are several orders of magnitude reduced by employing the proposed parallel architecture, rather than sequentially running the algorithm on an embedded ARM-CPU-based platform. |
| Keywords |
Prediction algorithms; Field programmable gate arrays; Real-time systems; Parallel architectures; Machine learning algorithms; Interpolation; Decision making; Data-driven control; field-programmable g |
| Universidad Loyola members |
|
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