Título Digital Fixed-point Low powered Area efficient Function estimation for implantable devices
Publicación externa No
Medio IEEE Access
Alcance Article
Naturaleza Científica
Cuartil JCR 2
Cuartil SJR 1
Web https://www.scopus.com/inward/record.uri?eid=2-s2.0-85133796765&doi=10.1109%2fACCESS.2022.3187439&partnerID=40&md5=a3f589459e5720a3bfe97748f93169ad
Fecha de publicacion 30/06/2022
ISI 000838451100001
Scopus Id 2-s2.0-85133796765
DOI 10.1109/ACCESS.2022.3187439
Abstract This article introduces a new multiplier-less 32-bit fixed point architecture for estimating complex non-linear functions based on adapted shift only series expansions. This novel hardware structure has been proposed for use as a dedicated core unit in implantable medical devices. Its implementation in FPGA produces a mean squared error of 0.23% over the functions <italic>sin</italic>(<italic>x</italic>),<italic>cos</italic>(<italic>x</italic>),<italic>eix</italic> and <italic>tan</italic>-1(<italic>x</italic>) when compared to unrestricted CPU implementations. These results are achieved with the use of only 133 sliced registers and 399 Look-up-tables (LUTs). Furthermore, the hardware performs extremely well in our hardware-in-the-loop real use case application for the detection of epilepsy by correctly detecting true positive seizures. When implemented into 130 nm technology via <italic>GOOGLE Sky130 PDK</italic> and <italic>Openlane</italic> EDA tools, the ASIC occupies a space of 0.0625 mm2 which represents a 47% reduction when compared to competitors. In addition, its power consumption is reduced to 6.46 mW at 100 MHz <italic>f<sub>o</sub></italic> and just 0.4 &#x03BC;W at 1KHz <italic>f<sub>o</sub></italic>. Author
Palabras clave Biomedical signal processing; Digital devices; Field programmable gate arrays (FPGA); Implants (surgical); Locks (fasteners); Low power electronics; Mathematical transformations; Table lookup; Timing
Miembros de la Universidad Loyola

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