ROMAINE, JAMES BRIAN, PEREIRA MARTÍN, MARIO
No
IEEE Access
Article
Científica
3.9
0.926
31/08/2022
000873916300001
2-s2.0-85137605457
In this manuscript the authors, design new hardware efficient combinational building blocks for a Multi Layer Perceptron (MLP) unit which eliminates the need for hardware generic Digital Signal Processing (DSP) units and also eliminates the need for on-chip block RAMs (BRAMs). The components were designed to minimise power and area consumption without sacrificing throughput. All designs were validated in a Field Programmable Gate Array (FPGA) and compared against unrestricted CPU-MATLAB implementations. Furthermore, a (2,2,2,2) MLP with back propagation was implemented and tested in a FPGA showing a total hardware utilisation of just 3782 LUTs, and no DSP or BRAMs. The MLP was also built in a Application Specific Integrated Circuit (ASIC) using a 130 nm technology by Skywater 130A. The results show that the area occupation was just 0.12~mm^{2} and consumed just 100 mW at 100 MHz input stimulus. © 2013 IEEE.
Application specific integrated circuits; Backpropagation; Deep neural networks; Digital signal processing; Field programmable gate arrays (FPGA); Implants (surgical); Integrated circuit design; Logic gates; MATLAB; Throughput; Timing circuits; Area optimization; Deep learning; Field programmable gate array; Field programmables; Low Power; Low power electroincs; Neural-networks; Power demands; Programmable gate array; Systems-on-Chip; System-on-chip